Our invention relates to packages for semiconductor chips in which solder layers are utilized to electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chips. More particularly, our invention relates to packages including such solder layers for power semiconductor chips or signal semiconductor chips.
A "power" semiconductor chip (hereinafter, simply "power chip"), as distinct from a "signal" semiconductor chip (discussed below), such as employed in a digital watch, generates waste heat during operation, typically in excess of about one watt. This heat must be removed lest the chip become overheated and damaged. For removing waste heat from a power chip, a typical prior art power chip package includes a metallic baseplate upon which the power chip is "thermally mounted," that is, attached to the baseplate with material of high thermal conductivity. The baseplate, in turn, is adapted to be mounted upon a metallic heat sink, typically of larger surface area than the metallic baseplate to provide rapid heat dissipation. To provide electrical access to the power chip, a metallic lead is connected to an integrally-formed electrode located on, for example, the upper side of the power chip via a solder layer, with any further integrally-formed electrodes on the upper surface of the power chip being connected to respective further leads via respective solder layers. An integrally-formed electrode on the lower side of the power chip is similarly connected to a lead via a solder layer if the power chip is electrically isolated from the metallic baseplate upon which it is mounted by a dielectric plate. Conversely, the metallic baseplate itself can serve as an electrical lead if the power chip is directly connected to it.
During typical operating cycles of the prior art power chip package, which involves heating (during conduction) and cooling (during non-conduction), the solder layers of the package are mechanically stressed, we believe, because the metallic baseplate (typically of copper) tends to thermally expand and contract to a much larger extent than the power chip (typically of silicon). Accordingly, after repeated thermal cycling of the power chip package, the solder layers become structurally degraded and thus less efficient at transferring waste heat away from the power chip. After continued thermal cycling of the power chip package, the solder layers degrade to a point where they are incapable of adequately transferring waste heat away from the power chip, with the result that the power chip overheats and undergoes damage.
Signal semiconductor chips (hereinafter, simply "signal chips") typically encounter thermal cycling during use. A signal chip may be used, for example, in an aircraft near the fuselage. At ground level, the temperature of such signal chip may reach about 100.degree. C., while at 70,000 feet altitude, the chip temperature is typically about -40.degree. C. We believe that such thermal cycling results in mechanical stress being imposed on solder layers utilized in a typical prior art package containing the signal chip, which solder layers electrically connect the conductors of a signal chip carrier, on which the signal chip is mounted, to conductors of a printed-circuit board, which typically accomodates many signal chip carriers. The mechanical stresses on the solder layers would then be responsible for premature failure of the signal chip package due to mechanical deterioration of the solder layers.